The present invention relates to a solid-state imaging device incorporating an A/D converter, and more particularly to a solid-state imaging device having a function for testing of the A/D converter. The present invention is applied to CMOS image sensors used for image sensor-embedded cellular phones, digital cameras, video cameras and the like, for example.
In recent years, various schemes have been proposed for signal readout in solid-state imaging devices. In general, a column parallel output type solid-state imaging device is often used in which one row of pixels in a pixel array are selected and pixel signals generated in the selected pixels are read in parallel via vertical signal lines. Also, a solid-state imaging device provided with a column A/D converter has appeared in which an A/D conversion circuit is provided for each vertical signal line for converting a pixel signal from analog to digital. For testing of such an A/D converter, a method in which a test circuit is provided inside the solid-state imaging device for testing has been proposed as in Japanese Laid-Open Patent Publication No. 2000-324404 (Patent Document 1), for example, in addition to a method of testing using optoelectronic conversion of pixels.
Hereinafter, an embodiment disclosed in Patent Document 1 will be described with reference to FIG. 10, which schematically illustrates a solid-state imaging device provided with a test circuit for testing an A/D converter.
As shown in FIG. 10, the solid-state imaging device 100 includes a timing generation circuit 2, a load transistor group 3, a pixel region 4, a vertical scanning circuit 5, a reference voltage generator 6, an A/D converter 7, a buffer (BUF) 8, a horizontal scanning circuit 9, a control circuit (CONT) 10, a test signal input circuit 11 and a test signal generation circuit 12. These circuits are formed on the same chip.
The test signal generation circuit 12 generates a test signal TEST for testing the A/D converter 7 under control with a control signal CN3 from the control circuit 10.
The test signal input circuit 11 allows the test signal TEST to enter vertical signal lines (14-1 to 14-n), whereby the test signal TEST is inputted into the A/D converter 7 via the vertical signal lines (14-1 to 14-n).
Switch transistors (11-1 to 11-n) of the test signal input circuit 11 turn ON/OFF under control with a control signal CN2 from the control circuit 10. The control circuit 10 is therefore provided with the function of turning the load transistor group 3 OFF to make 1s the impedance of the vertical signal lines (14-1 to 14-n) high and the function of controlling the test signal input circuit 11 at least during the test period, in addition to the function of controlling the reference voltage generator 6.
The control circuit 10 turns the load transistor group 3 OFF with a control signal CN1, and controls the test signal input circuit 11 with the control signal CN2 to permit the test signal TEST to enter the vertical signal lines (14-1 to 14-n).
In testing of the A/D converter 7, the control circuit 10 turns the load transistor group 3 OFF with the control signal CN1. Note that at this time pixel cells 13 are also OFF and thus the impedance of the vertical signal lines (14-1 to 14-n) becomes high.
The test signal generation circuit 12 outputs the test signal TEST in response to the control signal CN3 from the control circuit 10. The test signal TEST is inputted into the A/D converter 7 via the test signal input circuit 11 and the vertical signal lines (14-1 to 14-n) with the control signal CN2 from the control circuit 10.
The A/D converter 7 compares the test signal TEST with a reference voltage VREF to convert the test signal TEST to a digital signal. The converted digital signal is outputted outside the solid-state imaging device 100, for example, via the buffer 8. By evaluating the outputted digital signal, the characteristics of the A/D converter 7 are measured.
As described above, in the solid-state imaging device 100 shown in FIG. 10, the test signal TEST is inputted into the A/D converter 7 via the vertical signal lines (14-1 to 14-n). Hence, when the area of the pixel region 4 is too large to neglect the effect of the load of the vertical signal lines (14-1 to 14-n), it will be difficult to send the test signal TEST to the A/D converter 7 as a highly precise signal (first problem).
When an analog signal processing circuit (for example, a circuit for amplifying analog signals from the pixel cells 13, etc.) is placed between the pixel region 4 and the A/D converter 7, the test signal TEST will be affected by this analog signal processing circuit. As a result, it will be difficult to send the test signal TEST to the A/D converter 7 as a highly precise signal (second problem).
A signal supplied to the A/D converter 7 must have two signal levels, as described in Japanese Laid-Open Patent Publication No. 9-247494 (Patent Document 2) and Japanese Laid-Open Patent Publication No. 2005-323331 (Patent Document 3); namely, a pixel reset signal level supplied from the pixel cells 13 to the A/D converter 7 via the vertical signal lines (14-1 to 14-n) when the pixel cells 13 is reset, and a pixel signal level supplied from the pixel cells 13 to the A/D converter 7 via the vertical signal lines (14-1 to 14-n) when a charge stored in a photodiode of each pixel cell 13 is read from the photodiode.
Also, the pixel reset signal level and the pixel signal level must be arranged in time series during one horizontal period or one horizontal blanking period, to allow these signal levels to be supplied to the A/D converter 7 at desired timing.
For the test signal TEST prepared for testing the A/D converter 7, it is also requested to have these two signal levels.
Assuming herein that the test signal corresponding to the pixel reset signal level is called a “reference signal” and the test signal corresponding to the pixel signal level is called an “amplitude signal”, the test signal TEST is composed of the two kinds of signals; the reference signal and the amplitude signal. This definition of the reference signal and the amplitude signal also applies to embodiments of the present invention described later.
In the timing chart shown in Patent Document 1, also, the test signal TEST is composed of two kinds of signals, the reference signal and the amplitude signal, arranged in time series although not specifically described in Patent Document 1. Hence, the test signal generation circuit 12 must generate the reference signal and the amplitude signal, and these signals must independently have a level of precision necessary for the A/D converter 7 or higher. If the amplitude signal is generated as a ramp signal, the test signal generation circuit 12 needs a circuit for generating a ramp signal, and this increases the circuit scale of the test signal generation circuit 12 (third problem).
Also, a test for checking the precision of signals generated by the test signal generation circuit 12 is necessary for each solid-state imaging device, and this increases the test time (Fourth problem).
To solve the third and fourth problems described above, Patent Document 1 additionally describes the case of providing the test signal generation circuit 12 outside the solid-state imaging device 100, namely, performing the testing with an IC tester. However, since the solid-state imaging device has only one pad for receiving a test signal from the IC tester, the IC tester is required to have a mechanism permitting switching of the test signal between the reference signal and the amplitude signal at desired timing as required during one horizontal period or one horizontal blanking period. In particular, in the case of generating the amplitude signal as a ramp signal, an IC tester excellent in response permitting quick return to the voltage value of the reference signal is necessary. This increases both the man-hour needed to develop an IC tester satisfying this requirement and the cost required for this development (fifth problem).
The IC tester is required to supply the reference signal and the amplitude signal to the A/D converter 7 at desired timing. For this purpose, the IC tester must synchronize the timing at which the reference signal and the amplitude signal are supplied to the solid-state imaging device 100 with the timing at which the reference signal and the amplitude signal lo are supplied to the A/D converter 7. In Patent Document 1, a solid-state imaging device operating at a comparatively low speed satisfies the above. However, for a solid-state imaging device in which an external clock is multiplied with a multiplication circuit to operate the A/D converter at high speed, as described in Patent Document 3, for example, it is difficult to synchronize the timing at which the reference signal and the amplitude signal are supplied to the solid-state imaging device 100 from the IC tester with the timing at which the reference signal and the amplitude signal are supplied to the A/D converter 7 (sixth problem).
To solve the fifth and sixth problems described above, there is a method in which the reference signal is used as the reset signal for the pixel cells 13, for example, although not specifically described in Patent Document 1. With this method, since the reset signal for the pixel cells 13 can be controlled with the timing generation circuit 2 and the test signal input circuit 11 can be controlled with the control circuit 10, both the generation timing of the reference signal and the external input timing of the amplitude signal are completed within the solid-state imaging device. The only thing left to do is therefore sending the ramp signal that is to be the amplitude signal from the IC tester at arbitrary timing. Hence, the fifth and sixth problems can be solved even with the technology of Patent Document 1. However, the use of the reference signal as the reset signal for the pixel cells 13 may raise the possibility that the voltage value of the reference signal may differ among the vertical signal lines (14-1 to 14-n) due to variations in the characteristics of the pixel cells 13. It is therefore difficult to make the voltage value of the reference signal agree with the 0-point voltage value of the amplitude signal supplied from the IC tester. As a result, high-precision testing with an amplitude signal having a small amplitude, in particular, will be difficult, causing a new problem.
Note that Patent Document 1 also demonstrates, as a method for testing the minimum to maximum values of the amplitude signal at one time, an example in which resistors are provided between the adjacent vertical signal lines (14-1 to 14-n) and two test signals generated by the IC tester are inputted via two pads of the solid-state imaging device. This is however disadvantageous in that a test for checking the characteristics of the individual A/D converters is not allowed and that a test for checking variations among the A/D converters is not allowed.